Timing recovery is an important function of most Ethernet systems. Because a transmitting (TX) device typically transmits data to a receiving (RX) device in an asynchronous manner (i.e., without an accompanying clock signal), the RX device may generate an internal clock signal that is both frequency-aligned and phase-aligned with the received data signal. FIG. 1 shows an exemplary communications system 100 with asynchronous clock recovery. A TX device 110 transmits a signal onto a communications channel 120, and a RX device 130 receives the signal from the channel 120. The RX device 130 includes an analog front end (AFE) 132, an equalizer (EQ) 134, and a clock recovery circuit (CRC) 136. The AFE 132 receives an analog data signal over the communications channel 120, and the equalizer 134 mitigates and/or eliminates intersymbol interference (ISI) in the analog data signal caused by the channel 120. The clock recovery circuit 136 may recover a clock signal (RX_clk) from the received data signal.
More specifically, the clock recovery circuit 136 may use phase and frequency information of the received data signal to align the phase and frequency of a locally-generated clock signal with the phase and frequency of the clock signal used by the TX device 110 (e.g., a transmit clock signal). For example, the clock recovery circuit 136 may adjust the frequency of its local receive clock signal to match the frequency of the transmit clock signal, for example, to correct for drift between the clock generators of devices 110. The clock recovery circuit 136 may also adjust the phase of the local receive clock signal to match the phase of the transmit clock signal, for example, so that an analog-to-digital converter (not shown for simplicity) within the Rx device 130 may sample each data symbol at its peak (e.g., to further reduce the effects of ISI).
Extracting phase and frequency information from a high-speed data signal may pose a number of challenges. For one example, higher-frequency data rates correlate with shorter symbol (peak) durations, and thus provide a smaller window within which the RX device 130 may accurately sample a received data signal (e.g., as compared with lower-frequency data rates). For another example, ISI is more pronounced at higher frequencies than at lower frequencies. Accordingly, if the frequency offset between the local receive clock signal and the transmit clock signal is above a limit value, then the equalizer 134 of the RX device 130 may be unable to properly mitigate the effects of ISI in the received data signal. As a result, the clock recovery circuit 136 typically scans through a series of fixed clock frequencies to ensure proper operation of the equalizer 134. However, scanning through the entire range of possible frequencies for a given communication protocol (e.g., ±200 ppm in 10 GBASE-KR Ethernet systems and ±600 ppm in PCIe systems) may consume a substantial amount of time and resources.